Highly-integrated system-on-chip (SoC) devices power a wide a variety of products to serve the demands of even wider variety of software applications. To meet these demands, SoC devices continue to increase in size and complexity. Though aided by advance semiconductor processing technologies and silicon-proven third-party intellectual property, the development of highly-integrated SoCs increases the burdens on design verification teams. In some cases, verification consumes the majority of an SoC development cycle.
SoC design verification approaches may vary. Optimized for speed, software development, hardware development, or system validation, each approach provides varying levels of observability and control. Field programmable gate array (FPGA) prototype systems, for example, may provide improved system execution time. Some FPGA SoC verification systems, nevertheless, lack the ability to isolate the root cause of discovered errors due to the lack of visibility into the signal values within the design. Common deficiencies on FPGA vendor-specific verification tools include access to a limited number of signals, and limited sample capture depth. Even combined with an external logic analyzer, FPGA vendor-specific verification tools lack sufficient capabilities to isolate root cause errors during SoC verification.
It is therefore desirable to have methods or apparatus that may meet the design verification demands of highly-integrated SoC devices in certain application or may provide SoC design verification systems having improved control and observability of signals on FPGA-based electronic prototype systems.